MAX107ECS+【PDF 6/21 页】IC ADC 6BIT 400MSPS DL 80-TQFP

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MAX107

designed for single-ended, low-phase noise sine-wave

clock signals with as little as 500mVp-p amplitude

(-2dBm).

Single-Ended Clock (Sine-Wave Drive)

Excellent performance is obtained by AC- or DC-cou-

pling a low-phase noise sine-wave source into a single

clock input (Figure 4). Essentially, the dynamic perfor-

mance of the converter is unaffected by clock-drive

power levels from -2dBm (500mVp-p clock signal

amplitude) to +10dBm (2Vp-p clock signal amplitude).

The MAX107 dynamic performance specifications are

determined by a single-ended clock drive of -2dBm

(500mVp-p clock signal amplitude). To avoid saturation

of the input amplifier stage, limit the clock power level

to a maximum of +10dBm.

Differential Clock (Sine-Wave Drive)

The advantages of differential clock drive (Figure 5)

can be obtained by using an appropriate balun or

transformer to convert single-ended sine-wave sources

into differential drives. Refer to Single-Ended Clock

Inputs (Sine-Wave Drive) for proper input amplitude

requirements.

LVDS, ECL and PECL Clock

The innovative input architecture of the MAX107 clock

also allows these inputs to be driven by LVDS-, ECL- or

PECL-compatible input levels, ranging from 500mVp-p

to 2Vp-p (Figure 6).

Timing Requirements

The MAX107 features a 6:12 demultiplexer, which

reduces the output data rate (including DREADY and

DOR signals) to one-half of the sample clock rate. The

demultiplexed outputs are presented in dual 6-bit two’s

complement format with two consecutive samples in

the primary and auxiliary output ports on the rising

Dual, 6-Bit, 400Msps ADC with On-Chip,

Wideband Input Amplifier

______________________________________________________________________________________

AGND

180

SIGNAL SOURCE

*TERMINATION OF THE UNUSED INPUT/OUTPUT (WITH 50

TO AGND) ON A

BALUN IS RECOMMENDED IN ORDER TO AVOID UNWANTED REFLECTIONS.

CLK+,

INI+,

INQ+

CLK-,

INI-,

INQ-

100pF

AGND

Figure 3. Single-Ended to Differential Conversion Using a Balun

AGND

FROM SIGNAL SOURCE

CLK+,

INI+,

INQ+

CLK-,

INI-,

INQ-

100pF

Figure 4. Single-Ended Clock Input With AC-Coupled Input

Drive (CLK, INI, INQ)

Figure 5. Differential, AC-Coupled Input Drive (CLK, INI, INQ)

AGND

TRANSMISSION LINES

TO 50

-TERMINATED

SIGNAL SOURCE

OR BALUN

CLK+,

INI+,

INQ+

CLK-,

INI-,

INQ-

100pF

TRANSMISSION LINES

LVDS LINE DRIVER

SIGNAL

SOURCE

INPUT

CLK+,

INI+,

INQ+

CLK-,

INI-,

INQ-

100pF

100

Figure 6. LVDS Input Drive (CLK, INI, INQ)

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